This invention relates to solar cells and the manufacture thereof.
Solar cells are fabricated by a veriety of methods, with the spin-on method being the most commonly used. According to this method, a doped silicon wafer or semiconductor substrate is mounted on a turntable and a liquid impurity, or dopant, is placed on the center of the wafer. The wafer is spun rapidly about its central axis to spread the dopant evenly across the upper surface of the wafer. Some of the dopant usually spills over the edge of the wafer during this fabrication step. After drying, the wafer is baked, causing the dopant to diffuse beneath the surface of the wafer and form a p-n junction. The large surface area on the top of the solar cell beneath which the p-n junction is formed is termed the active region of the cell. It is here that light energy is converted to electrical energy as a result of the photovoltaic effect. Electron-hole pairs are generated in the active region and are drawn out to electrodes on the top and bottom sides of the cell as useful current. The charge generated as these pairs are separated by the p-n junction creates a potential difference between the electrodes on the solar cell. The dopant which spilled over the side of the wafer during the spinning step, however, is the source of short circuit paths on the edge of the wafer connecting one side of the p-n junction to the other. Typically, these conductive paths are removed mechanically or chemically so that the p-n junction which is exposed on the edge surface of the silicon wafer is not short circuited.
Two other methods commonly used in the manufacture of solar cells are the gaseous and planar source method. In the gaseous method, the doped silicon wafer is placed in a furnace and a gas containing the desired impurity is passed over it. The impurity is deposited from the gas onto the surface of the wafer and the heat from the furnace causes the impurity to diffuse beneath the surface of the wafer. In the planar source process, the doped silicon wafer is placed inside a furnace in close proximity with a disc containing the desired impurity. As the temperature is elevated within the furnace, the impurity particles migrate from the impurity source to the wafer and diffuse beneath its surface. During the diffusion step in both the gaseous and planar source methods, the impurity diffuses into the wafer along the peripheral edge as well as the top surface. The spilled dopant which is diffused along the peripheral edge of the wafer is the source of the short circuit paths which cause the p-n junction to be short circuited and the top and bottom surfaces of the wafer to be electrically connected.
The formation of short circuit paths could be eliminated by masking or covering the edges of the wafer during application and diffusion of the impurity or dopant. This is highly undesirable, however, because of the time and expense associated with the extra steps required to position protective masks around the edge of the wafer. A typical method for removing the short circuit paths from the peripheral edge of the wafer involves grinding away the side surface of the wafer. Another common method for removing the short circuit paths involves etching them away along with part of the side surface of the wafer.
Both of these methods for removing the short circuit paths are unsatisfactory because, after the short circuit paths have been removed by etching or grinding, the p-n junction along the edge of the wafer is left exposed to the environment. Semiconductor devices are very sensitive to surface contaminants since leakage paths form readily where dust particles or other contaminants settle onto the exposed p-n junction. If either edge grinding or etching is employed to remove the short circuit paths from the edge of the wafer, therefore, it is preferable that the edge surface be sealed afterwards to protect the exposed p-n junction from the effects of surface contaminants with attendant uneconomical increase in cost and fabrication time.
Accordingly, it is an object of this invention to provide a solar cell which has an isolation member suitable for isolating the active region from short circuit paths along the peripheral edge of the cell.
Another object of this invention is to provide a solar cell having the intersection of the p-n junction and the surface of the cell sealed beneath the isolation member.
A further object of this invention is to provide a method for manufacturing solar cells whereby short circuit paths need not be removed mechanically or chemically from the unfinished edge of the cell.